This invention relates to an high capacity DRAM device having a smaller cell size as well as having a higher storage capacity. This process also relates to a process for preparing xe2x80x9cmemoriesxe2x80x9d and other semiconductor devices with smaller dimensions and precise controls. In particular, this invention relates to a process for preparing DRAM""s having a smaller cell size with high storage capacities and the cell layout of a high density DRAM product having a capacity as high as four gigabits.
In recent years, in the area of semiconductor memory devices such as DRAM, 4M and 16M DRAMs have been mass-produced, and 64M DRAMs have been studied. In DRAMs, the typical three dimensional structures such as a trench type and a stack type have been developed. The trench type is manufactured in a groove provided on the semiconductor substrate, and the stack type is formed by laminating in three dimensions the conductive layers on the surface of the semiconductor substrate. The trench type has a flatter surface than the stack type, providing advantages for lithography but has serious operating disadvantages. The operation voltage is changed by leakage of current and punch-through between adjacent trenches. Electron-hole pairs generated by xcex1-particles transmitted inside the substrate are also a problem.
The stack type is formed by laminating element layers on the substrate, and the fabrication process sequence is simpler than for the trench type and does not have the operating deficits noted above. As a result, the stack type is more attractive than the trench type.
A limiting factor in the construction of stack type DRAMs in smaller cell sizes is the minimum storage capacity of 25 fF required for proper operation of a DRAM, that is, the cell capacity required per cell and the practical limit of photolithography techniques for achieving smaller dimensions. As the memory device is made to be more highly integrated and thus smaller in size, the area occupied by each cell is reduced, thus reducing the area available for each capacitor. To be functionally operable, the capacitor must have a large capacity, even as the size of the memory cell is reduced.
The chip size of a DRAM product is determined by the formula:
Chip Area=AP+AM
Where:
AP is the Area of Peripheral circuits; and
AM is the Area of total Memory cells and is calculated by the formula:
AM=Total Bits (or density)xc3x97a Cell Area
Normally, AM occupies more than 55 percent of the total chip area in a high density DRAM. Because the smaller the chip size, the lower the production cost, every effort is directed to reducing the cell size. It can be shown that the memory cell size can be estimated by the formula:
Cell Area=2xc3x97(AP+2xcex4)xc3x97WP/AE
xe2x80x83Wherein:
AP=Active Pitch;
xcex4=Spacing of a bit line contact to the word line due to alignment limitations of photolithography (alignment errors);
WP=Word Line Pitch; and
AE=Area Efficiency.
In the produce and process of this invention, AE can be greater than previously known configurations, being above 80% and as high as about 100%.
Prior art approaches have focused on reducing the Cell Area by scaling but have reached limits in size reduction and tolerances due to the limits of photolithography, process techniques, and the need to make a capacitors having capacities greater than 25 fF. Similar constraints have limited the Area Efficiency for a typical 16 M DRAM to less than 80 percent.
It is an object of the present invention to provide a process for manufacturing a semiconductor device which provides component widths and spacings of in a range down to 1000 xc3x85 and smaller in horizontal planes by using the existing optical stepper or other advanced conventional lithographic exposure systems and even smaller dimensions in a range down to 700 xc3x85 using more advanced X-ray and more precise RIE techniques.
It is another object of this invention to provide a smaller DRAM cell structure which provides a theoretical efficiency of 100 percent.
It is a still further object of this invention to enable the construction of DRAMs having a density of up to four gigabits per device without sacrificing the cell capacity.
A further object of this invention is the provision of a DRAM having components which are entirely constructed in straight line structures, avoiding stress points, and yielding a more stable, low leakage product.
It is a still further object of this invention to provide a DRAM having word and active line arrays each of which are straight, have a uniform width, and have a uniform, minimum spacing from adjacent members of their respective arrays, the word and bit lines being in a configuration perpendicular to each other. In summary, one process of this invention is to produce a desired width of a product material in small dimensions in a range down to 800 xc3x85. The process comprises the following steps:
a) depositing a form material on the surface of a product material;
b) removing a portion of the form material by vertical etching using photolithography to leave a sidewall of said form material;
c) depositing a layer of masking material over the form material and product material, the layer of masking material having a thickness correlating to said desired width of product material;
d) removing masking material by vertical RIE until the form material is exposed, leaving a predetermined width of masking material, and removing the form material until the underlying product material is exposed;
e) removing portions of the product material which are not protected by the masking material to leave a desired width of product material corresponding to the width of the masking material; and
f) removing the masking material, leaving a desired width of said product material.
The form material can be nitride, the masking material can be oxide, and the product material is a conductor such as doped polysilicon. Examples of suitable products formed by this process are word lines and capacitor plates.
Another process of this invention forms a small spacing d between widths of material. This can be useful for reducing spacings between capacitor plates, conductors or transistors, and in reducing the size of field oxide areas, for example. It can also yield products such as bit lines or word lines with reduced widths. The process for forming a desired space between adjacent portions of a product material having a width e comprises the following steps:
a) depositing a form material on the surface of a product material;
b) removing a center portion of the form material by vertical etching using photolithography to leave form materials having widths W with opposed sidewalls spaced apart by a distance D which is greater than the desired spacing d by 2xcex94;
c) depositing a layer of masking material over the form material and product material, the layer of masking material having a thickness correlating to xcex94;
d) removing masking material by vertical RIE until the form material is exposed, leaving xcex94 widths of masking material contacting each of the opposed sidewalls of the form material;
e) removing form material by etching;
e) removing portions of the product material which are not protected by the masking material; and
f) removing the form material and the masking material, leaving adjacent pairs of adjacent widths of product material, each having a width e of in a range down to 800 xc3x85, the desired spacing d between adjacent pairs of product material being in a range down to 700 xc3x85; and a spacing W between adjacent widths of a product material.
In this process, each of the form material, masking material and product material is a member independently selected from the group consisting of nitride, oxide, conductor and laminate combinations thereof. Preferably, the form material and the masking material are not the same member, and the masking material and the product material are not the same member. For example, the form material include nitride, oxide, or combinations thereof; the masking material can be oxide; and the product material can be doped polysilicon or metal.
In one embodiment, the form material is nitride, the masking material is oxide, and the product material is a conductor. The product material can doped polysilicon.
The adjacent widths of product material can be word lines capacitor plates, for example.
Another embodiment of the process of this invention forms a desired spacing d in small dimensions in a range down to 700 xc3x85 between adjacent widths of a product material. It comprises the following steps:
a) depositing a form material on the surface of a product material;
b) forming an array of photolithographic masking materials spaced apart by a distance D;
c) removing portions of the form material by vertical etching to leave an array of form materials with opposed sidewalls spaced apart by a distance D which is greater than spacing d by 2xcex94 and removing the photolithographic masking materials;
c) depositing a layer of second masking material over the form material and product material, the layer of second masking material having a thickness correlating to xcex94;
d) removing second masking material by vertical RIE until the form material is exposed, leaving xcex94 widths of opposed second masking material contacting each of the opposed sidewalls of the form material, the distance between the opposed widths of second masking material being in a range in a range down to 700 xc3x85.
In one embodiment of this process, the form material, masking material and product material are each individually selected from the group consisting of nitride, oxide, conductor and laminate combinations thereof. Preferably, the form material and the masking material are not the same member and the masking material and the product material are not the same member.
In another embodiment of the process, the form material, masking material and product material are each individually selected from the group consisting of nitride, oxide, conductor and laminate combinations thereof, but the form material and the masking material are not the same member.
The process can be followed by the step of removing portions of the product material which are not protected by the masking material by RIE, and optionally, all or only part of the product material not protected by the masking material can be removed.
The process can be followed by an alternative steps of removing the product material by RIE, and removing the form material and the masking material by etching, leaving the product material widths separated by the desired space d.
In one embodiment, the product material is a layer of nitride supported by a silicon substrate and the masking material is polysilicon.
The process can be followed by the following additional steps:
oxidizing the exposed surfaces to effect oxidation of the polysilicon and the underlying substrate silicon; and
removing the form material and polysilicon to leave a silicon substrate having field oxide portions with widths in a range down to 1000 xc3x85.
The products of this invention includes memory having a plurality of linear straight word lines which have a uniform relative spacing and width; a plurality of active spaces which are linear, straight and have a uniform width and spacing; and combinations thereof. The product can be a stacked capacitor DRAM device.
Another memory device of this invention has a plurality of linear straight bit lines; a plurality of linear straight word lines which have a uniform relative spacing and width; a plurality of active spaces which are linear, straight and have a uniform width and spacing, or any combinations of any two or three thereof. The products can be a stacked capacitor DRAM device.
Another memory device of this invention has active area contacts which are isolated from adjacent active area contacts by non-conducting layers, the active area contacts having small widths of in a range down to 700 xc3x85. A conductive landing pad layer contacts each of the active area contacts and overlaps a portion of the adjacent non-conducting layer, thereby enlarging the effective surface area of each area contact. Such a memory device can also include a parallel array of word lines extending in a direction, wherein the active area contact is a bit line contact, and the landing pad extends from the active area to a position displaced therefrom in said direction. Such a device can a stacked capacitor DRAM device.
Another process of this invention forms a cup-shaped capacitor plate for a stacked capacitor memory device. The process comprises the following steps:
a) depositing a conductive layer in electrical contact with an active capacitor contact area of a substrate;
b) depositing a upper layer of nitride, oxide or combination thereof on the surface of the conductive layer;
c) forming a mask on the surface of the upper layer, the outer boundary of the mask positioned to define the inner walls of the capacitor;
d) removing the upper layer and optional portions of the conductive layer by RIE to a depth which correlates to the sidewall thickness of the capacitor and removing the mask;
e) depositing a layer of oxide material on the surface obtained in step (d);
f) removing oxide by RIE until oxide is removed from the upper layer, leaving a shoulder of mask oxide on the surface of the upper layer and the conductive layer;
g) removing the upper layer by etching and removing portions of the conductive layer which are not covered by the shoulder of mask oxide by RIE, leaving the sidewalls and floor of the capacitor;
h) removing mask oxide by etching to leave a cup-shaped capacitor plate;
I) depositing a layer of dielectric on the surface of the capacitor plate; and
j) forming a conductive layer on the layer of dielectric to form a capacitor.
In this process, a portion of the conductive layer can be supported on a layer of support oxide, and step (h) can comprise comprises mask oxide and support oxide by etching to leave a cup-shaped capacitor plate, at least a portion of the underside of the floor thereof being available for capacitor surface. In this process, the width of the shoulder of mask oxide can be in a range down to 700 xc3x85, for example.
A still further process of this invention is an array of transistors. It comprises the following steps
a) depositing a layer of gate material on a layer of gate oxide supported by active silicon substrate;
b) depositing an upper layer comprising nitride or oxide or combinations thereof on the gate material;
c) forming an array of photolithography masked areas defining spaces between adjacent transistor gates on the upper layer, the distances between adjacent masked areas is D;
d) removing the upper layer not covered by the masking areas by RIE and removing the photoresist;
e) depositing mask oxide on the upper surface obtained in step (d);
f) removing mask oxide by RIE, leaving shoulders of oxide mask adjacent the upper layer having a thickness xcex94;
g) removing upper layer by etching and removing gate material by RIE to leave an array of mask oxide protected gates;
h) removing mask oxide by etching, leaving an array of gates with width e.
In this process, the silicon substrate between adjacent gates formed in step (g) can be weakly doped by ion implantation and can be followed by the following additional steps:
i) a layer of masking oxide is deposited on the product of step (h);
j) masking oxide is removed by RIE to leave shoulders of mask oxide adjacent the gates and exposed areas of active substrate between the shoulders; and
k) exposed areas of active substrate are doped by ion implantation.
A still further process of this invention smaller, precise field oxide in a semiconductor device. It comprises the following steps:
a) depositing successive pad oxide, polysilicon and upper nitride layers on a silicon substrate;
b) forming resist mask portions on the nitride layer by photolithography to define the field oxide area and portions of the nitride to remain and removing the areas of nitride and a partial polysilicon unprotected by the mask portions by RIE, and removing the resist mask portions;
c) depositing a masking layer of polysilicon on the upper surfaces of the product of step (b);
d) removing the masking polysilicon by RIE to leave shoulders of mask polysilicon and exposed areas of nitride between the shoulders;
e) exposing the product of step (d) to oxidation to grow field oxide in the exposed areas of pad oxide.
Other features and advantages of the invention will be apparent from the following description taken in connection with the accompanying drawings.